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What is the purpose and technique of DMA logic?
Direct memory access (DMA) is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit (CPU). Without DMA, [ when the CPU is using programmed input/output, it is typically fully occupied for the entire duration of the read or write operation, and is thus unavailable to perform other work. With
DMA, the CPU initiates the transfer, does other operations while the transfer is in progress, and receives an interrupt from the DMA controller when the operation is done. This feature is useful any time the CPU cannot keep up with the rate of data transfer, or where the CPU needs to perform useful work while waiting for a relatively slow I/O data transfer. Many hardware systems use DMA, including disk drive controllers, graphics cards, network cards and sound cards. DMA is also used for intra-chip data transfer in multi-core processors. Computers that have DMA channels can transfer data to and from devices with much less CPU overhead than computers without a DMA channel. Similarly, a processing element inside a multi-core processor can transfer data to and from its local memory without occupying its processor time, allowing computation and data transfer to proceed in parallel. ]
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Asked 10/1/2012 3:44:03 PM
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Should DMA access to main memory be given higher priority than processor access to main memory?
Weegy: yes, Hence DMA has a higher priority than CPU. (More)
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Asked 10/1/2012 1:46:48 PM
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What is the purpose and technique of DMA logic?
Weegy: During any given bus cycle, one of the system components connected to the system bus is given control of the bus. This component is said to be the master during that cycle and the component it is communicating with is said to be the slave. [ The CPU with its bus control logic is normally the master, but other specially designed components can gain control of the bus by sending a bus request to the CPU. After the current bus cycle is completed the CPU will return a bus grant signal and the component sending the request will become the master. Taking control of the bus for a bus cycle is called cycle stealing. Just like the bus control logic, a master must be capable of placing addresses on the address bus and directing the bus activity during a bus cycle. The components capable of becoming masters are processors (and their bus control logic) and DMA controllers. Sometimes a DMA controller is associated with a single interface, but they are often designed to accommodate more than one interface. The 8086 microprocessor receives bus requests through its HOLD pin and issues grants from the hold acknowledge (HLDA) pin. A request is made when a potential master sends a 1 to the HOLD pin. Normally, after the current bus cycle is complete the 8086 will respond by putting a 1 on the HLDA pin. When the requesting device receives this grant signal it becomes the master. It will remain master until it drops the signal to the HOLD pin, at which time the 8086 will drop the grant on the HLDA pin. One exception to the normal sequence is that if a word, which begins at an odd address is being accessed, then two bus cycles are required to complete the transfer and a grant will not be issued until after the second bus cycle. When a DMA controller becomes master it places an address on the address bus and sends the interface the necessary signals to cause it to put data on, or receive data from, the data bus. Since the DMA controller determines when the bus request is ... (More)
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Asked 10/1/2012 3:07:13 PM
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What is the purpose of DMA logic?
Weegy: The DMA logic unit controls the connection of selected one of the I/O peripheral devices to the memory subsystem for direct transfer or data therebetween, when the I/O peripheral devices place a request. [ The DMA logic unit includes a base address register, a base count register and a DMA controller. ] User: What is the purpose and technique of DMA logic? (More)
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Updated 10/1/2012 4:10:09 PM
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The techniques of DMA logic are:

- using caching techniques to keep data pinned as long as possible, producing overhead reductions for applications that repeatedly - communicate in the same memory area
pipelining memory pinning operations and data transfer (as done on Infiniband or Myrinet)
deferring memory pinning out of the critical path, thus hiding the latency increase
entirely removing the need for pinning (as Quadrics does)
Added 10/1/2012 4:10:13 PM
What are the differences between an interrupt and a trap? Provide an example of each. What is their importance?
Weegy: An interrupt is a hardware-generated event, usually caused by an I/O device requesting service. A trap, on the other and, is a software-generated interrupt. Traps are caused by 1) system calls and 2) exceptional software conditions (e.g. [ Divide by 0). Other than the source and function, processing of traps and interrupts is the same. ] (More)
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Asked 10/1/2012 3:57:28 PM
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